The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2026
Filed:
Sep. 16, 2021
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Shunpei Yamazaki, Setagaya, JP;
Takayuki Ikeda, Atsugi, JP;
Tatsuya Onuki, Atsugi, JP;
Hitoshi Kunitake, Isehara, JP;
Yasuhiro Jinbo, Isehara, JP;
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Abstract
A memory device having large memory capacity is provided. A highly reliable memory device is provided. A semiconductor device includes a first conductive layer extending in a first direction, a structure body extending in a second direction intersecting with the first direction, a first insulating layer, and a second insulating layer. The structure body includes a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer. In an intersection portion of the first conductive layer and the structure body, the third insulating layer, the semiconductor layer, and the functional layer are placed concentrically around the second conductive layer in this order. The first insulating layer and the second insulating layer are stacked in the second direction. The functional layer and the first conductive layer are placed between the first insulating layer and the second insulating layer. The second conductive layer, the third insulating layer, and the semiconductor layer include a portion positioned inside a first opening provided in the first insulating layer and a portion positioned inside a second opening provided in the second insulating layer.