Switching scheme for operating a three-level buck converter in a two-level buck converter mode

Abstract

Certain aspects of the present disclosure generally relate to a three-level buck converter operating in a two-level buck converter mode with a delay between deactivating transistors when transitioning between charge and discharge phases. For example, certain aspects provide a power supply circuit generally including: a first transistor and a second transistor coupled between an input node of the power supply circuit and a switching node of the power supply circuit; a third transistor and a fourth transistor coupled between a reference potential node of the power supply circuit and the switching node of the power supply circuit; and logic configured to control activation states of the first transistor, the second transistor, the third transistor, and the fourth transistor. In some aspects, the activation states of the first transistor and the second transistor are configured to be switched at different times between the charge phase and the discharge phase.