The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Sep. 15, 2023
Applicants:

SK Hynix Inc., Icheon-si, KR;

SK Hynix Nand Product Solutions Corp., Rancho Cordova, CA (US);

Inventors:

Pengfei Huang, San Jose, CA (US);

Zion Kwok, Burnaby, CA;

Fan Zhang, San Jose, CA (US);

Assignees:

SK HYNIX INC., , KR;

SK HYNIX NAND PRODUCT SOLUTIONS CORP., Rancho Cordova, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/52 (2006.01); G11C 7/14 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G11C 7/14 (2013.01); G11C 29/785 (2013.01);
Abstract

This application is directed to data validation in an electronic device having a memory device. The memory device receives an inquiry for a validity condition of a page of the memory device from a memory controller that is coupled to the memory device in a memory system. In response to the inquiry, the memory device selects a subset of the page of the memory device to represent the page. The subset of the page stores a set of memory data. The memory device obtains integrity data corresponding to the set of memory data, applies a plurality of validation operations on the set of memory data and the integrity data corresponding to the set of memory data to generate a plurality of validity results. The memory device determines an error parameter of the page locally based on the plurality of validity results and provides the error parameter to the memory controller.


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