The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Apr. 01, 2024
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Thomas Ziaja, Palo Alto, CA (US);

Uma Durairajan, Palo Alto, CA (US);

Dinesh R. Amirtharaj, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/32 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G06F 11/27 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/408 (2006.01); G11C 29/12 (2006.01); G11C 29/36 (2006.01); G11C 29/42 (2006.01);
U.S. Cl.
CPC ...
G11C 29/32 (2013.01); G11C 7/1039 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 29/36 (2013.01); G11C 29/42 (2013.01); G01R 31/3172 (2013.01); G01R 31/31723 (2013.01); G01R 31/3177 (2013.01); G01R 31/3185 (2013.01); G01R 31/318536 (2013.01); G01R 31/318541 (2013.01); G01R 31/318544 (2013.01); G01R 31/318547 (2013.01); G01R 31/318566 (2013.01); G01R 31/3187 (2013.01); G06F 11/27 (2013.01); G11C 7/1051 (2013.01); G11C 7/22 (2013.01); G11C 11/4082 (2013.01); G11C 2029/3202 (2013.01);
Abstract

An integrated circuit (IC) includes a memory array with M rows of N storage elements that has an N-bit wide parallel input and output, and a 1-bit wide array scan input and output. A memory built-in self-test (MBIST) circuit is connected to the memory array to generate test addresses and N-bit wide test data. Functional circuitry with a functional address bus and N-bit wide functional data path is linked to the memory array. Control circuitry enables a serial test mode for shifting data through the storage elements, a MBIST mode for test data access, and a normal operation mode for functional data access. This IC design offers versatile memory testing and operational capabilities.


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