The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Oct. 24, 2024
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Kiran Ananda Patil, Austin, TX (US);

Monica M. Tang, Santa Clara, CA (US);

Zsolt Mathe, Bellevue, WA (US);

Nisheeth Srivastava, Sammamish, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 11/0772 (2013.01); G06F 11/3037 (2013.01);
Abstract

Systems and methods are provided for detecting memory hazards in memory, such as in massively parallel and distributed systems. In examples, a memory hazard logic detects access of a memory by a device communicatively coupled to the memory. The memory hazard logic identifies a memory access type and a memory address range being accessed, based on information obtained when monitoring a memory access transaction between the device and the memory. The memory hazard logic determines whether the memory access type on the memory address range is subject to memory access rules contained in a rules table. If so, the memory hazard logic determines whether the memory access type matches a memory access rule associated with each memory address in the memory address range. For each such memory address, the memory hazard logic notifies the device regarding a memory hazard triggered by the memory access transaction.


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