The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Nov. 21, 2024
Applicant:

Infortrend Technology, Inc., New Taipei, TW;

Inventors:

Yen-Chen Wu, New Taipei, TW;

Ying-Wen Lin, New Taipei, TW;

Chih-Min Hsiao, New Taipei, TW;

Chun-Hsiang Lin, New Taipei, TW;

Assignee:

Infortrend Technology, Inc., New Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0664 (2013.01); G06F 3/0604 (2013.01); G06F 3/0689 (2013.01);
Abstract

The present invention discloses a data access method and a storage subsystem implementing the method. The storage subsystem includes two storage virtualization controllers (SVC, SVC), a backplane, a physical storage device (PSD), and a clock generation circuit. The clock generation circuit is mounted on the backplane and provides a dedicated clock signal to the PSD. The PSD has a single port, and the lanes of the single port are divided into two half portions, each of which is coupled to one of the two storage virtualization controllers (SVC, SVC). Therefore, the present invention eliminates the need for additional intermediate components to couple the single-port PSD to the two storage virtualization controllers (SVC, SVC). This leads to simplified wiring and reduced costs, and the PSD will not be affected by failures of the intermediate components, thereby enhancing the redundancy architecture of the storage subsystem.


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