The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Sep. 27, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Chulyong Jang, Anyang-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/3171 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 2224/02125 (2013.01); H01L 2224/0214 (2013.01); H01L 2224/0215 (2013.01); H01L 2224/08059 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16237 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A method of manufacturing a semiconductor package includes: forming through-vias extending from a front side of a semiconductor substrate into the substrate; forming, on the front side of the semiconductor substrate, a circuit structure including a wiring structure electrically connected to the through-vias; removing a portion of the semiconductor substrate so that at least a portion of each of the through-vias protrudes to a rear side of the semiconductor substrate; forming a passivation layer covering the protruding portion of each of the through-vias; forming trenches recessed along a periphery of a corresponding one of the through-vias; removing a portion of the passivation layer so that one end of each of the through-vias is exposed to the upper surface of the passivation layer; and forming backside pads including a dam structure in each of the trenches, the dam structure being spaced apart from the corresponding one of the through-vias.


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