The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Nov. 25, 2021
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Shingo Eguchi, Atsugi, JP;

Tomoya Aoyama, Atsugi, JP;

Daiki Nakamura, Atsugi, JP;

Kenichi Okazaki, Atsugi, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/12 (2023.01); H10K 59/80 (2023.01); H10K 71/20 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1201 (2023.02); H10K 59/873 (2023.02); H10K 71/231 (2023.02);
Abstract

A high-resolution, high-definition, or large display apparatus is provided. A metal mask is placed over an EL layer and film deposition is performed with the metal mask, whereby an island-shaped counter electrode is formed. Then, the EL layer is processed using the counter electrode as a hard mask. Alternatively, after an EL layer and a counter electrode are formed over an entire surface, processing using a metal mask is performed. An insulating layer that electrically insulates adjacent pixel electrodes from each other is positioned between adjacent light-emitting devices. A resist mask is formed over the insulating layer. A plurality of EL layers and a plurality of counter electrodes overlapping each other over the insulating layer are partly removed using the resist mask, whereby part of the insulating layer is exposed. Thus, the adjacent light-emitting devices are electrically insulated from each other over the insulating layer.


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