The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2026
Filed:
Aug. 28, 2023
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/30 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01);
Abstract
A semiconductor device may include a peripheral circuit portion, a memory cell array disposed over the peripheral circuit portion and including a vertical conductive line, a bonding pad structure between the peripheral circuit portion and the memory cell array, a dielectric pad layer configured to cover the top of the vertical conductive line of the memory cell array, and a higher-level pad that is coupled to the vertical conductive line through the dielectric pad layer.