The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Jun. 20, 2023
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventor:

Hsiang-Lan Lung, Ardsley, NY (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10B 63/845 (2023.02);
Abstract

A 3D bit cost scalable memory device includes a stack of layers and a via electrode extending vertically through the stack of layers. The layers include a controllable conductivity layer and an electrode layer. The electrode layer has a conductor portion and a separator portion that separates the via electrode from the conductor portion of the electrode layer. At least a storage portion of the controllable conductivity layer is in electrical series between the via electrode and the conductor portion of the electrode layer. The via electrode comprises, for example, tungsten (W). The controllable conductivity layer comprises, for example, an ovonic threshold switch material. The conductor portion of the electrode layer comprises, for example, carbon (C).


Find Patent Forward Citations

Lung, Hsiang-Lan. (2026). 3d bit cost scalable memory (U.S. Patent No. 12563748). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12563748

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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