The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Dec. 21, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Daewon Ha, Seoul, KR;

Kyunghwan Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); G11C 11/22 (2006.01); H10B 51/40 (2023.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); G11C 11/2275 (2013.01); H10B 51/40 (2023.02); H10D 64/689 (2025.01);
Abstract

A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode on the substrate and extending in a second direction, and a plurality of channel layers on the active region. The plurality of channel layers are spaced apart from each other in a third direction perpendicular to an upper surface of the substrate. The device includes a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers include at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers has a different coercive voltage. The device includes source/drain regions in recess regions in which the active region is recessed, the source/drain regions are on both sides of the gate electrode, and the source/drain regions are in contact with the plurality of channel layers.


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