Idle tone mitigation using clock jitter

Abstract

A circuit includes: a capacitive micro-electromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal; a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, where the VCO is configured to generate a frequency modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO; a random number generator configured to generate random numbers; and a phase modulator configured to generate a phase modulated clock signal by modulating a phase of a system sampling clock signal in accordance with the random numbers, where the FTD converter is configured to generate a digital signal in accordance with the frequency modulated signal and the phase modulated clock signal, and is configured to sample the digital signal by the phase modulated clock signal to generate a digital output signal of the FTD converter.