The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Oct. 10, 2023
Applicant:

Aydeekay Llc, Aliso Viejo, CA (US);

Inventors:

Artur Langner, Aliso Viejo, CA (US);

Colin Ramsay, Aliso Viejo, CA (US);

Assignee:

AyDee Kay, Aliso Viejo, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/14 (2014.01); H03K 5/19 (2006.01); H04L 12/28 (2006.01); H04L 12/40 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); H03K 5/19 (2013.01); H04L 12/28 (2013.01); H04L 12/40 (2013.01); H03K 2005/00084 (2013.01);
Abstract

An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.


Find Patent Forward Citations

Loading…