Methods of balancing clock skew in stacked semiconductor devices

Abstract

Methods of fabricating a semiconductor device include securing a first die to a second die. The first die includes a first clock signal path from a clock source to a first load and passing through a tap point electrically connected to a clock output. The second die includes a second clock signal path from a clock input to a second load. The methods also include connecting the clock input of the second die to the clock output of the first die. A first divergence between the tap point and the first load is substantially the same as a second divergence from the tap point through the clock input and the clock output to the second load. Various other methods, devices, and systems are also disclosed.