The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Jun. 26, 2023
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Jojy Jose, Singapore, SG;

Soon Hwei Tan, Singapore, SG;

Hariom Rai, Bangalore, IN;

Arun Khamesra, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/335 (2006.01); H02M 1/00 (2006.01); H02M 1/08 (2006.01); H03K 17/10 (2006.01); H03K 17/691 (2006.01);
U.S. Cl.
CPC ...
H02M 3/33592 (2013.01); H02M 1/0045 (2021.05); H02M 1/083 (2013.01); H03K 17/102 (2013.01); H03K 17/691 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A method comprising controlling operation, by a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a low-side field-effect transistor (FET). In response to controlling operation of the low-side FET, the method further includes triggering a zero-cross detection circuit. The method further includes measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit. The method further includes measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit. The method further includes adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.


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