The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Dec. 21, 2023
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Xuan Tian, Shanghai, CN;

Liang Li, Shanghai, CN;

Peter Chu, Shanghai, CN;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G01R 31/52 (2020.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G01R 31/52 (2020.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/344 (2013.01); G11C 16/34 (2013.01); G11C 29/52 (2013.01);
Abstract

The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory device also includes control circuitry that is configured to perform a programming operation or an erasing operation. During the programming or erasing operation, the circuitry is configured to, while applying a voltage to at least one selected word line of the plurality of word lines, measure a word line resistance/capacitance (WLRC). The circuitry is also configured to, in response to the WLRC being inside of a predetermined range, continue the programming or erasing operation. The circuitry is further configured to, in response to the WLRC being outside of the predetermined range, establish that the memory block has a short and quarantine the memory block.


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