The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2026
Filed:
Jun. 16, 2023
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Cagri Erbagci, Pittsburgh, PA (US);
Burak Erbagci, Pittsburgh, PA (US);
Lalit Gupta, Fremont, CA (US);
Jesse San-Jey Wang, Santa Clara, CA (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/1096 (2013.01);
Abstract
Negative bit line voltage assist mechanisms for multi-bank machine memories utilizing multiple local IO drivers include a shared boost capacitor configured to generate a negative bit line voltage assist for write operations by local IO drivers, where the boost capacitor is configured to selectively couple to one of the local IO drivers during the write operation.
Erbagci, Cagri. (2026). Shared metal wire capacitance for negative bit-line (U.S. Patent No. 12562200). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12562200
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile