Reconfigurable streaming processor for security computations

Abstract

A computing system includes a streaming engine and a graph core. The streaming engine includes an array of compute units (CUs), an array of crossbar switches, and a configurable interconnect circuit. The CUs perform logical operations on operands. The crossbar switches forward outputs of one or more CUs to inputs of one or more neighboring CUs. The configurable interconnect circuit forwards an output of at least one of the CUs to an input of at least one of the crossbar switches. The graph core programs the streaming processor to perform a security computation by selectively configuring the CUs to perform a plurality of respective logical operations in a programmable order to define a flow of logical operations to be performed by the CUs that effects the security computation, and configuring the crossbar switches and the interconnect circuit to perform the logical operations by traversing the CUs according to the flow.