The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Jan. 15, 2024
Applicant:

Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

Qunyi Yang, Beijing, CN;

Fan Yang, Beijing, CN;

Xu Wang, Beijing, CN;

Zhongxiang Cheng, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/27 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G06F 11/27 (2013.01); G06F 11/2236 (2013.01);
Abstract

A chip with built-in verification is shown. The signals of key nodes within the chip are collected as operational information. Verification hardware built into the chip includes a plurality of registers, which are programmed to define a branch-type trigger condition. The branch-type trigger condition is formed by sequence-related events. The verification hardware includes an arithmetic module that generates a debugging prompt in response to the branch-type trigger condition defined in the plurality of registers being satisfied by the operational information.


Find Patent Forward Citations

Yang, Qunyi. (2026). Chip with built-in verification and method for built-in chip verification (U.S. Patent No. 12561219). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12561219

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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