The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Dec. 01, 2022
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Bilal Chehab, Leuven, BE;

Pieter Schuddinck, Nieuwerkerken, BE;

Julien Ryckaert, Schaerbeek, BE;

Pieter Weckx, Bunsbeek, BE;

Assignee:

Imec vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H01L 23/528 (2013.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01);
Abstract

Example embodiments relate to complementary field-effect transistor (CFET) devices. An example CFET device includes a bottom FET device. The bottom FET device includes a bottom channel nanostructure having a first side surface oriented in a first direction. The bottom FET device also includes a second side surface oriented in a second direction opposite the first direction. Further, the bottom FET device includes a bottom gate electrode configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure. The bottom gate electrode includes a side gate portion arranged along the first side surface of the bottom channel nanostructure. The CFET device also includes a top FET device stacked on the bottom FET device. The top FET device includes channel layers, a gate electrode, and gate prongs. Additionally, the CFET device includes a top gate contact via. Further, the CFET device includes a bottom gate contact via.


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