The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2026
Filed:
Jan. 30, 2024
Nokia Solutions and Networks Oy, Espoo, FI;
Paul Brown, Wakefield, CA;
Alex Chan, Ottawa, CA;
Daniel Anav, San Jose, CA (US);
Jonathan Montag, San Jose, CA (US);
NOKIA SOLUTIONS AND NETWORKS OY, Espoo, FI;
Abstract
A multi-layer printed circuit board (PCB), includes a first plurality of layers, each having a plurality of signal traces disposed thereon, a second plurality of layers, each having a voltage plane disposed thereon, and a plurality of plated-through-hole vias disposed between a first surface of the multi-layer PCB and a second surface of the multi-layer PCB, wherein each plated-through-hole via includes a conductive barrel, wherein a first layer of the first plurality of layers includes a backdrill clearance region around a first plated-through-hole via in which no signal traces are disposed, and a first voltage plane on a first layer of the second plurality of layers is in contact with the conductive barrel of the first plated-through-hole via. In various embodiments, portions of the barrel of a plated-through-hole via are removed by, for example, backdrilling. Various embodiments advantageously provide improvements to signal-to-reference overlap, and to power plane current-carrying capacity.