The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jul. 10, 2023
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Evgeny Paltin, Montreal, CA;

Gwenael Poitau, Montreal, CA;

Hamidreza Farmanbar, Ottawa, CA;

Eran Goldstein, Montreal, CA;

Assignee:

DELL PRODUCTS L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/00 (2006.01); H04L 41/16 (2022.01); H04W 72/12 (2023.01);
U.S. Cl.
CPC ...
H04W 72/12 (2013.01); H04L 41/16 (2013.01);
Abstract

The technology described herein is directed towards having a trained artificial intelligence/machine learning (AI/ML) model provide an accurate physical layer (PHY/L1) processing time prediction that a MAC (medium access control) scheduler can use to schedule resources more efficiently. The AI/ML model is trained with large, easily obtainable datasets of configurations of tasks, to return an accurate processing time estimate based on input configuration data representing task data to be scheduled. The model can map a sequence of configurations for consecutive time slots to a sequence of expected processing times for each slot, while capturing temporal information for previously scheduled but not yet processed tasks, making it possible to optimize task execution sequences by choosing an optimal permutation for configurations/tasks. A real time scheduler can test multiple task hypotheses to select the most optimal one for a time slot.


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