The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2026
Filed:
Apr. 10, 2024
Renesas Electronics America Inc., Milpitas, CA (US);
Greg Anton Armstrong, Ottawa, CA;
Renesas Electronics America Inc., Milpitas, CA (US);
Abstract
Systems and methods for synchronizing networks are described. A phase monitor circuit can determine at least one phase offset among a plurality of reference clock signals. A timing circuit can generate an output clock signal using a primary reference clock. The primary reference clock can be among the plurality of reference clock signals. The timing circuit can determine failure of the primary reference clock. The timing circuit can, in response to the failure of the primary reference clock, generate the output clock signal using a specific phase offset and a secondary reference clock for the PLL. The specific phase offset can be among the at least one phase offset determined by the phase monitor circuit, the specific phase offset is between the primary reference clock and the secondary reference clock, and the secondary reference clock can be among the plurality of reference clock signals.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile