The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2026
Filed:
May. 15, 2024
Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Ming Hu, Beijing, CN;
Wenhui Gao, Beijing, CN;
Yonglin Guo, Beijing, CN;
Ziyang Yu, Beijing, CN;
Tiaomei Zhang, Beijing, CN;
Miao Wang, Beijing, CN;
Quanyong Gu, Beijing, CN;
Shilong Wang, Beijing, CN;
Jingwen Zhang, Beijing, CN;
Jian Li, Beijing, CN;
Jianpeng Wu, Beijing, CN;
Tianyi Cheng, Beijing, CN;
Zhiliang Jiang, Beijing, CN;
Gukhwan Song, Beijing, CN;
Hai Zheng, Beijing, CN;
Haigang Qing, Beijing, CN;
Xiangdan Dong, Beijing, CN;
Yi Zhang, Beijing, CN;
Rui Wang, Beijing, CN;
Taofeng Xie, Beijing, CN;
Haijun Qiu, Beijing, CN;
Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan, CN;
BOE Technology Group Co., Ltd., Beijing, CN;
Abstract
A pixel circuit includes a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit and a storage sub-circuit. The driving sub-circuit is configured to control a circuit brand between a second node and a third node to be closed and opened under control of a voltage of a first node. The compensation sub-circuit is configured to control a circuit branch between the first node and the third node to be closed and opened in response to a first scanning signal received at a first scanning signal terminal. The reset sub-circuit is configured to transmit a first initialization signal received at a first initialization signal terminal to the first node in response to a reset signal received at a reset signal terminal. The storage sub-circuit is configured to store voltages of the first node and the second node.