Systems and methods for embedding graphs using systolic algorithms

Abstract

An accelerated version of a node-weighted path distance algorithm is implemented on a microprocessor coupled to a digital processor. The algorithm calculates an embedding of a source graph into a target graph (e.g., hardware graph of a quantum processor). The digital processor causes the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in a working embedding of a node, compute a minimum distance to neighboring logic blocks from each seeded logic block, set the distance to neighboring logic blocks as the minimum distance plus the weight of the seeded logic block, increment the accumulator value by the weight of the seeded logic block, increment the accumulator value by the distance, determine the minimum distance logic block by computing the minimum accumulated value, compute distances to the minimum distance logic block; and read distances from all logic blocks into local memory.