Integrated circuit interconnect shape optimizer

Abstract

Systems, devices, and methods for optimization of conducting interconnects are described. A method includes receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect. The method includes generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information. The method includes determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information. The method also includes generating an updated integrated circuit layout based at least in part on the individual contribution.