Collaborative hardware-software technique for increasing resilience to bit-flips

Abstract

A memory management unit (MMU) of a computing device obtains an indication that an algorithm is being used by a program to generate, for storage within a first subset of bits of an entry of an address translation data structure, a value generated from a second subset of bits of the entry. During a traversal of the data structure entry to perform a virtual-to-physical address translation, the MMU applies the algorithm to the second subset of bits. In response to determining that the result obtained from the algorithm by the MMU does not match the value stored in the first subset of bits, the MMU initiates a remedial action associated with bit-flips.