The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Mar. 06, 2023
Applicant:

Ieit Systems Co., Ltd., Shandong, CN;

Inventors:

Yuanli Wang, Shandong, CN;

Hongwei Kan, Shandong, CN;

Jiangwei Wang, Shandong, CN;

Le Yang, Shandong, CN;

Assignee:

IEIT SYSTEMS CO., LTD., Shandong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/24 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4221 (2013.01); G06F 13/24 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/24 (2013.01);
Abstract

Provided are a PCIe interrupt processing method and apparatus, a device and a non-transitory readable storage medium, relating to the technical field of computers. The PCIe interrupt processing method comprises: a currently generated internal interrupt signal is acquired; a PCIe interrupt type supported by a current FPGA is determined according to an interrupt vector signal output by a PCIe IP core, so as to determine a corresponding target interrupt processing mechanism according to the PCIe interrupt type; and the internal interrupt signal is processed by means of the target interrupt processing mechanism, and a processing result is input to the PCIe IP core, such that the PCIe IP core sends an interrupt message packet to a central processing unit on the basis of the processing result. The technical solution expands the compatibility of an FPGA with processor interrupts, facilitating the implementation of FPGA logic platform construction.


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