The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

May. 04, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ayelet Hen, Tel-Aviv, IL;

Eilon Regev, Tel-Aviv, IL;

Or Davidi, Tel-Aviv, IL;

Yotam Avraham Platner, Tel-Aviv, IL;

Tal Heller, Tel-Aviv, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/30029 (2013.01); G06F 9/5033 (2013.01);
Abstract

A method of statically allocating memory for a computer program includes splitting a computational graph associated with a plurality of static memory allocation constraints into a plurality of subgraphs; determining a memory allocation for each combination of subgraphs of the plurality of subgraphs using an SAT solver and a plurality of Boolean conditions that formalize the plurality of static memory allocation constraints; subdividing a subgraph of the plurality of subgraphs into a plurality of tiles, when the memory allocation for that subgraph cannot satisfy a hardware memory size constraint of the plurality of static memory allocation constraints; performing a performance analysis on all possible subgraphs and plurality of tiles; selecting a combination of subgraphs whose plurality of tiles has a best overall performance; and determining a memory allocation for the plurality of tiles for the selected combination of subgraphs using the SAT solver.


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