Memory device with row address repeater controlling memory bank

Abstract

Disclosed is a memory device, which may include memory banks including a plurality of memory cells, row address repeaters that transfer a row address to the memory banks, and control logic that controls data input/output of the memory banks. The memory banks may be grouped into a plurality of bank groups, and the row address repeaters may be grouped into a plurality of repeater groups respectively corresponding to the plurality of bank groups. The control logic may control the row address repeaters according to activation status of the plurality of bank groups.