Memory control apparatus and memory control method

Abstract

A memory control apparatus that controls access to a DRAM including a plurality of banks, the apparatus comprising: a first generation unit that generates an access command in response to an access request to the DRAM and stores the access command in a buffer; a second generation unit that generates a refresh request specifying a bank to the DRAM; and an issuance unit that issues a DRAM command to the DRAM, based on the access command stored in the buffer and the refresh request generated by the second generation unit, wherein the second generation unit determines a target bank of the refresh request from among banks remaining after excluding, from the plurality of banks, a bank that is an access target of the access command stored in the buffer and having a dependency relationship that needs to maintain issuance order.