The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Sep. 20, 2023
Applicant:

Semiconductor Components Industries, Llc, Scottsdale, AZ (US);

Inventors:

Shiva Shanthan Veluri, Bangalore, IN;

Anirudh Oberoi, New Delhi, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 3/26 (2006.01); G05F 1/575 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
G05F 3/262 (2013.01); G05F 1/575 (2013.01); H03F 3/45475 (2013.01);
Abstract

A reference buffer circuit for buffering a reference voltage is disclosed. The reference buffer circuit includes an input circuit that may generate a replica of the reference voltage. A feedback circuit may generate a charging current using a current mirror circuit and a bias current. A value of the charging current may be greater than a value of the bias current. The feedback circuit may provide a buffered version of the reference voltage at a reference node using the charging current and the replica voltage. An output stage circuit may sink a compensation current from the reference node.


Find Patent Forward Citations

Veluri, Shiva. (2026). Buffer circuit for capacitive loads (U.S. Patent No. 12554280). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12554280

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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