The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Mar. 25, 2022
Applicants:

Chengdu Boe Display Sci-tech Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yijing Zhao, Beijing, CN;

Chao Xie, Beijing, CN;

Yudan Yang, Beijing, CN;

XI Yang, Beijing, CN;

Tao Xiong, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H10D 86/40 (2025.01);
U.S. Cl.
CPC ...
G02F 1/136263 (2021.01); H10D 86/441 (2025.01);
Abstract

An array substrate includes a substrate, a first gate line, a plurality of data lines, a plurality of first pixel electrodes, a plurality of first transistors and a plurality of first capacitive lines that are all disposed on the substrate. A data line and the first gate line cross, and are insulated from each other. An orthographic projection of a first capacitive line on the substrate is overlapped with an orthographic projection of a first pixel electrode on the substrate. The first capacitive line includes a first conductive segment that is proximate to the first gate line and is provided with a first break therein. An orthographic projection, on the substrate, of a portion of the first conductive segment located on a side of the first break away from the middle subsection is overlapped with an orthographic projection of a second electrode of a first transistor on the substrate.


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