The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jan. 13, 2023
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Oseob Jeon, Seoul, KR;

Seungwon Im, Bucheon, KR;

Rajani Kumar Thirukoluri, Munich, DE;

Roveendra Paul, Dublin, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49562 (2013.01); H01L 23/5386 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/40225 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73221 (2013.01);
Abstract

In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.


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