The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

May. 16, 2023
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Stefan Landis, Grenoble, FR;

Yorrick Exbrayat, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/573 (2013.01); H01L 21/027 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01);
Abstract

A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level and an interconnection level including vias, includes providing the first level and a dielectric layer, forming an etching mask on the dielectric layer, randomly depositing particles on the etching mask, and forming a lithographic layer having opening patterns. The mask layer is etched through opening patterns to form mask openings, then the dielectric layer is etched through the mask openings, so as to obtain functional via openings and degraded via openings. The via openings are filled so as to form the vias of the interconnection level, the vias including functional vias at the functional openings and malfunctional vias at the degraded openings.


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