The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jun. 01, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yong Zhuo, Beijing, CN;

Yanxia Xin, Beijing, CN;

Hongwei Hu, Beijing, CN;

Zheng Bao, Beijing, CN;

Xueping Li, Beijing, CN;

Yihao Wu, Beijing, CN;

Xiaoyun Wang, Beijing, CN;

Zhongqian Guo, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10K 59/121 (2023.01); H10K 59/12 (2023.01); H10K 59/131 (2023.01); H10K 71/70 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/1201 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H10K 71/70 (2023.02);
Abstract

Provided are a display substrate, a testing method therefor and a preparation method therefor, and a display panel, which are used for improving the success rate of transistor testing. The display substrate comprises a base substrate and a pixel circuit, wherein the pixel circuit comprises an active layer, a first gate insulating layer, a first gate electrode layer, a second gate insulating layer, a second gate electrode layer, a first interlayer insulating layer, a source/drain electrode layer, and a second interlayer insulating layer. The pixel circuit is divided into a plurality of transistors, and further comprises a gate electrode contact hole and a source/drain electrode contact hole. The source/drain electrode layer comprises a gate electrode test pad which is electrically connected to the first gate electrode layer by means of the gate electrode contact hole, and a source electrode and a drain electrode which are electrically connected to the active layer by means of the source/drain electrode contact hole. The second interlayer insulating layer is provided with a gate electrode test hole and a source/drain electrode test hole, wherein the gate electrode test hole exposes the gate electrode test pad, and the source/drain electrode test hole exposes part of an area in the source/drain electrode layer other than the gate electrode test pad.


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