The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Mar. 24, 2022
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yudiao Cheng, Beijing, CN;

Yanwei Lu, Beijing, CN;

Weiyun Huang, Beijing, CN;

Lili Du, Beijing, CN;

Yuanjie Xu, Beijing, CN;

Zhuoran Yan, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/62 (2010.01); H01L 25/075 (2006.01); H01L 25/16 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 20/857 (2025.01); H10H 29/14 (2025.01);
U.S. Cl.
CPC ...
H10H 20/857 (2025.01); H01L 25/0753 (2013.01); H01L 25/167 (2013.01); H10D 86/443 (2025.01); H10D 86/60 (2025.01); H10H 29/142 (2025.01);
Abstract

Provided is a display panel, including: a substrate, a connection line, a first pixel drive circuit, a first insulative layer, and first light-emitting devices. The substrate includes a light-transmissive display region and a conventional display region at least partially surrounding the light-transmissive display region. The connection line and the first pixel drive circuit are disposed on the substrate. The connection line is electrically connected to the first pixel drive circuit. The first pixel drive circuit is disposed in the conventional display region. The first insulative layer is disposed on a side, distal from the substrate, of the connection line and is provided with first via holes arranged in arrays. The first light-emitting devices are disposed on a side, distal from the substrate, of the first insulative layer and arranged in arrays in the light-transmissive display region and electrically connected to the connection lines via the first via holes.


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