The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2026
Filed:
Feb. 17, 2022
Applicant:
Sunrise Memory Corporation, San Jose, CA (US);
Inventors:
George Samachisa, Atherton, CA (US);
Vinod Purayath, Sedona, AZ (US);
Wu-Yi Henry Chien, San Jose, CA (US);
Eli Harari, Saratoga, CA (US);
Assignee:
SUNRISE MEMORY CORPORATION, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); G11C 11/22 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 30/701 (2025.01); G11C 11/223 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10D 30/0415 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 30/711 (2025.01);
Abstract
By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors ('FeFETs'), thereby providing a very high-speed, high-density memory array.