The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jan. 13, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Henry Litzmann Edwards, Garland, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/65 (2025.01); H01L 21/225 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/17 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/65 (2025.01); H01L 21/2253 (2013.01); H10D 30/0281 (2025.01); H10D 30/603 (2025.01); H10D 62/393 (2025.01); H10D 84/83 (2025.01);
Abstract

An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.


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