The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Apr. 27, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Siyeon Cho, Yongin-si, KR;

Hyunmook Choi, Suwon-si, KR;

Jihong Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02);
Abstract

In a method of manufacturing a semiconductor device, an insulation layer and a first gate electrode layer are alternately and repeatedly formed on a substrate in a first direction perpendicular to an upper surface of the substrate to form a mold layer. The first gate electrode layer includes silicon doped with impurities having a first conductivity type. An opening is formed through the mold layer to expose the upper surface of the substrate. Portions of the first gate electrode layers adjacent to the opening are removed to form gaps, respectively. Horizontal channels are formed in the gaps, respectively. Each of the horizontal channels includes silicon doped with impurities having a second conductivity type. A vertical gate structure extending in the first direction is formed in the opening. A memory channel structure is formed through the mold layer to contact the upper surface of the substrate.


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