Methods and circuits for controlling multicycle path in serializer interface

Abstract

Various example embodiments herein provide methods, circuits, and systems, for controlling a multicycle path in a serializer interface. The method includes determining a desired delay window of a multicycle data path in a serializer interface by sampling at least one step response from serializer delay replica circuitry at an edge of a first clock signal and a gating signal, in response to synchronizing a second clock signal with a negative edge of the first clock signal, configuring a polarity of a latch in a subsequent serializer of a serializer chain based on the determined desired delay window, and controlling the multicycle data path in the serializer interface based on the configured polarity of the latch in the subsequent serializer of the serializer chain.