The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jun. 10, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Sreeharipriya Garikipati, Hyderabad, IN;

Pragya Pande, Lucknow, IN;

Ankur Mehrotra, Greater Noida, IN;

Rohit Singh, Hyderabad, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0008 (2013.01); H03K 19/20 (2013.01);
Abstract

Aspects of the disclosure are directed to dc power consumption optimization in an extended reality (XR) device with thermal constraints. In accordance with one aspect, the disclosure includes performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.


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