The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Nov. 08, 2022
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Andrew J. Howlett, Edinburgh, GB;

Michael Chandler-Page, Chesterfield, GB;

David P. Singleton, Edinburgh, GB;

Erich P. Zwyssig, Edinburgh, GB;

Assignee:

Cirrus Logic Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03G 3/30 (2006.01); H03F 3/04 (2006.01); H04R 3/04 (2006.01);
U.S. Cl.
CPC ...
H03G 3/30 (2013.01); H03F 3/04 (2013.01); H03G 3/3005 (2013.01); H04R 3/04 (2013.01); H03G 2201/103 (2013.01); H04R 2430/01 (2013.01);
Abstract

An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.


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