The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jan. 16, 2024
Applicant:

Powerx Semiconductor Corporation, Hsinchu County, TW;

Inventors:

Jui Teng Chan, Hsinchu County, TW;

Yong Cyuan Chen, Hsinchu County, TW;

Chung-Kang Wu, Hsinchu County, TW;

Assignee:

PowerX Semiconductor Corporation, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/38 (2007.01); H02M 3/158 (2006.01); H03K 5/13 (2014.01);
U.S. Cl.
CPC ...
H02M 1/38 (2013.01); H02M 3/158 (2013.01); H03K 5/13 (2013.01);
Abstract

The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.


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