The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Oct. 11, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sheshashayee K Raghunathan, Bangalore, IN;

Charles Gates, Poughkeepsie, NY (US);

Kerim Kalafala, Rhinebeck, NY (US);

Steven Joseph Kurtz, Austin, TX (US);

Morgan D. Davis, Rochester, MN (US);

Debra Dean, Cary, NC (US);

Chris Cavitt, Queensbury, NY (US);

Chaitra M Bhat, Bangalore, IN;

Richard William Taggart, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/31 (2020.01); G06F 119/10 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 30/398 (2020.01); G06F 2119/10 (2020.01); G06F 2119/12 (2020.01);
Abstract

A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.


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