The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Mar. 31, 2023
Applicants:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

William A. Moyes, Austin, TX (US);

Carlos Javier Moreira, Markham, CA;

Kathirkamanathan Nadarajah, Markham, CA;

Keith Graham Shaw, Vancouver, CA;

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI TECHNOLOGIES ULC, Markham, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/72 (2013.01); H04L 9/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 21/72 (2013.01); H04L 9/14 (2013.01); G06F 2212/1052 (2013.01);
Abstract

A processing system includes one or more storage encryption circuits (SIECs) interconnected with one or more input/output (I/O) devices and a system memory. Each SIEC is configured to encrypt and decrypt data as the data passes between the I/O devices and the system memory. To this end, an SIEC includes slots each associated with respective memory addresses of the system memory. Each slot provides an aperture to the associated memory addresses such that the I/O devices use these apertures to indirectly target the associated memory addresses. As the data targeting the memory addresses associated with an aperture passes through an SIEC, the SIEC encrypts or decrypts the data using cryptographic keys stored on the SIEC.


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