Trace cache that supports multiple different trace lengths

Abstract

Disclosed techniques relate to storing wide traces in a trace cache. In some embodiments, prediction circuitry predicts directions of control transfer instructions. Instruction cache circuitry may cache instructions sequentially in cache lines that store up to a first number of instructions. Trace cache circuitry may identify traces of instruction, store identified traces having up to the first number of instructions in first trace storage circuitry, and store identified traces having up to a second, greater number of instructions in second trace storage circuitry. This may advantageously allow longer traces to be executed from the second trace storage circuitry (without extensive changes to the instruction cache and processor front end, in some embodiments, due to the limited trace length for the first trace storage circuitry).