The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jun. 04, 2024
Applicant:

Siliconch Systems Pvt Ltd, Karnataka, IN;

Inventors:

Shubham Paliwal, Kanpur, IN;

Rakesh Kumar Polasa, Bengaluru, IN;

Burle Naga Satyanarayana, Andhra Pradesh, IN;

Satish Anand Verkila, Bengaluru, IN;

Alagesan Mani, Tamil Nadu, IN;

Assignee:

SILICONCH SYSTEMS PVT LTD, Bangalore, IN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318314 (2013.01); G01R 31/2834 (2013.01); G01R 31/2849 (2013.01);
Abstract

The present disclosure relates to a method and a system for creating and debugging a silicon production test program for a semiconductor device. The method includes running a pre-silicon test program for testing a semiconductor device under test based on a plurality of test plan parameters. The method includes converting the pre-silicon test program from a hardware description language to a high-level programming language in response to determining that the pre-silicon test program is created in the hardware description language. The method includes integrating the pre-silicon test program with a bench board test program or an automated test equipment (ATE) test program, and mapping Application Programming Interface (API) resources available in the pre-silicon test program to one or more resources available in the bench board test program or the ATE test program during integration. The method includes testing and debugging the semiconductor device under test using an emulation platform.


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