The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2026
Filed:
Sep. 01, 2022
Applicant:
Ngk Insulators, Ltd., Nagoya, JP;
Inventors:
Seiya Inoue, Handa, JP;
Tatsuya Kuno, Nagoya, JP;
Assignee:
NGK INSULATORS, LTD., Nagoya, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01J 37/32 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67109 (2013.01); H01J 37/32532 (2013.01); H01J 37/32642 (2013.01); H01J 37/32724 (2013.01); H01L 21/68785 (2013.01);
Abstract
A wafer placement table includes a ceramic base having a wafer placement surface on its top surface and incorporating an electrode, a cooling base provided on a bottom surface side of the ceramic base, and a refrigerant flow channel groove provided in the cooling base so as to open at a bottom surface of the cooling base.
Inoue, Seiya. (2026). Wafer placement table, and member for semiconductor manufacturing apparatus, using the same (U.S. Patent No. 12543527). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12543527
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile