The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Mar. 25, 2022
Applicants:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Riken, Saitama, JP;

Inventors:

Takahiro Kawamura, Kanagawa, JP;

Hiroki Tojinbara, Kanagawa, JP;

Takaki Hatsui, Saitama, JP;

Shinichi Yoshida, Kanagawa, JP;

Keiichi Nakazawa, Kanagawa, JP;

Hikaru Iwata, Kanagawa, JP;

Kazunobu Ota, Kanagawa, JP;

Takuya Maruyama, Kanagawa, JP;

Hiroaki Ishiwata, Kanagawa, JP;

Chihiro Arai, Kanagawa, JP;

Atsuhiro Ando, Kanagawa, JP;

Toru Shirakata, Kanagawa, JP;

Hisahiro Ansai, Kanagawa, JP;

Satoe Miyata, Kanagawa, JP;

Ryu Kamibaba, Kanagawa, JP;

Yusuke Uesaka, Kanagawa, JP;

Yukari Takeya, Kanagawa, JP;

Assignees:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

RIKEN, Saitama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/18 (2025.01); H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H10F 39/1892 (2025.01); H10F 39/811 (2025.01);
Abstract

A first light-receiving element of an embodiment of the disclosure includes: a semiconductor substrate including a photoelectric conversion region; a first first electrically-conductive region provided at a first surface interface of the semiconductor substrate and coupled to a first electrode; a second first electrically-conductive region provided around the first first electrically-conductive region and coupled to a second electrode, at the first surface interface; a third first electrically-conductive region in an electrically floating state provided around the second first electrically-conductive region, at the first surface interface; a first second electrically-conductive region having a different electrically-conductive type between the first first electrically-conductive region and the second first electrically-conductive region, at the first surface interface; and a fourth first electrically-conductive region provided at least between the first first electrically conductive region and the first second electrically-conductive region and having an impurity concentration lower than the first first electrically-conductive region, near the first surface interface.


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